The EpiNex® Process

A Smarter Way to Make Silicon Wafers.

EpiNex® grows precision-engineered silicon wafers directly from gas, eliminating conventional ingot growth and wire sawing. The process enables precise control of wafer thickness and doping profiles while dramatically improving silicon utilization.

50–150 μmPrecision thickness and resistivity control

p-type & n-typeEngineered doping profiles

Up to 40× lower oxygenCompared with conventional CZ silicon

Seed. Grow. Release.

Direct gas-to-wafer manufacturing process

NexWafe seed preparation equipment — 01 / Seed
Prepare a reusable silicon seed with a porous separation layer.

NexWafe in-line CVD deposition equipment, photograph rotated 90 degrees — 02 / Grow
Grow the wafer epitaxially, precisely controlling thickness and doping profiles.

EpiNex wafer detachment from the reusable seed wafer — 03 / Release
Separate the finished wafer and reclaim the seed for reuse.

Precision Engineering.
Built Into Every Wafer.

Ultra-Thin Precision & Uniformity

Precise thickness and resistivity control at ultra-thin dimensions, supporting tighter efficiency distributions.

Engineered Doping for Radiation Resilience

Precisely controlled boron doping gradients create internal electric fields that reduce radiation-induced power loss.

Low Oxygen. No Gallium Dependency.

Ultra-low oxygen content reduces the risk of boron–oxygen degradation, without gallium doping.

Explore EpiNex® Engineered Wafers →

Silicon utilization

Precision-Grown. Not Cut from an Ingot.

EpiNex® wafers are grown directly to their required thickness, rather than sliced from an ingot. This eliminates conventional wire-saw kerf losses.

The Thinner the Wafer, the Greater the Silicon Savings

As wafer thickness decreases, conventional slicing losses account for an increasing share of silicon consumption. Additional thinning processes can further increase these losses.

EpiNex®CZ / wafering / wet thinning

Efficiency = finished wafer silicon ÷ (finished wafer silicon + non-recoverable loss)

Finished wafer thickness70 µm

150 µm100 µm50 µm

EpiNex® 80%

70 µm in the wafer17 µm lost (seed process)

CZ wafer 44%

70 µm in the wafer59 µm lost (kerf, etch, scrap)30 µm lost to thinning

1.8× more silicon used with EpiNex at this thickness

Methodology

Material-loss values are process-model assumptions, not measured production data.

Silicon utilization = finished-wafer silicon ÷ (finished-wafer silicon + non-recoverable silicon loss).
EpiNex®: modeled non-recoverable silicon loss of 17 µm per wafer, associated with the reusable seed process.
CZ: modeled slicing loss of 59 µm per wafer, plus additional thinning from 100 µm for wafers thinner than 100 µm.

Source: NexWafe internal analysis.

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